(a) Field of the Invention
The present invention relates to a semiconductor memory device having a word line activation block, and more particularly to the arrangement of the word line activation block with respect to a row address decoder.
(b) Description of the Related Art
A DRAM is known which includes a plurality of memory cell arrays each having a plurality of subword lines separately from main word lines for specifying the row address of a selected memory cell in each memory cell array. The subword lines are generally activated by a higher voltage signal than the operational voltage.
FIG. 1 shows a conventional DRAM having such a configuration, wherein the DRAM has four memory cell arrays ARY1 to ARY4 and peripheral circuits such as logic circuits etc. FIG. 2 shows one of the memory cell arrays ARY1 to ARY4 shown in FIG. 1. The memory cell array, for example, memory cell array ARY1 includes a plurality of memory cell blocks MCA1 to MCA16 arranged in a matrix, a plurality of main address decoder blocks XDA1 to XDA4 each corresponding to one of the memory cell blocks MCA1 to MCA16, a plurality of subword driver sections SWD1 to SWD20 each two sandwiching therebetween a corresponding one of memory cell blocks MCA1 to MCA16, a plurality of sense amplifier blocks SAA1 to SAA20 each two sandwiching therebetween a corresponding one of the memory cell blocks MCA1 to MCA16, and a plurality of word line activation blocks WA1 to WA16.
The subword drivers SWD1 to SWD20 receive output signals from the row address decoder blocks XDA1 to XDA4, i.e., main word signals including the information of significant bits of the row address signal, and word line activation signals from the word line activation blocks YAD1-YAD4. The word line activation signal includes the information of less significant bits of the row address signal and a higher voltage level with respect to the main address signal. Each of the subword drivers SWD1 to SWD20 outputs a signal having the higher voltage level through one of the subword lines. For this purpose, the word line activation blocks WA1 to WA16 are arranged in the peripheral area adjacent to the column address decoders to activate the activation signal lines extending normal to the main word lines.
In the conventional DRAM as described above, it is difficult to find room for the activation signal lines for transferring output activation signals from the word line activation blocks WA1 to WA16 within the sense amplifier blocks SAA1 to SAA4. Thus, as shown in FIG. 3 depicting a part of the memory cell array of FIG. 2, the area for the memory cell block MCA1 is extended in the row direction to pass the activation signal lines WS1 to WS4 which by-pass the area for the sense amplifier blocks SAA1.
In addition, in a virtual channel DRAM which includes a data buffer array and a SRAM adjacent to the sense amplifiers, the area for the word line activation blocks WA1 to WA16 is generally occupied by the data buffer array. Thus, it is desired to relocate the word line activation blocks WA1 to WA16 into an area other than the area for the data buffer array in the virtual channel DRAM.
It is an object of the present invention to provide a semiconductor memory device which is capable of arranging the word line activation blocks and the activation signal lines at suitable locations.
The present invention provides a semiconductor memory device comprising:
a memory cell array including an array of memory cells arranged in a matrix, a plurality of subword lines each specifying a row of the memory cells, and a plurality of data lines for specifying a column of the memory cells;
a column address decoder block including a plurality of column address decoders each responding to a column address signal to specify a corresponding one of the data lines;
a row address decoder block including a plurality of row address decoders each for responding to significant bits of a row address signal to generate a main word signal;
a plurality of main word lines each disposed for a corresponding one of the address decoders for transferring the main word signal;
a word line activation block including a plurality of word line activation decoders each for responding to less-significant bits of the row address signal to generate a subword signal;
a plurality of word line activation lines each disposed for a corresponding one of the word line activation decoders to transfer the subword signal; and
a subword driver block for responding to the main word signal and the subword signal to specify one of the subword lines,
wherein the word line activation block is disposed adjacent to at least some of the row address decoders.
In accordance with the semiconductor memory device of the present invention, this arrangement of the word line activation blocks affords a wider design choice for the semiconductor memory device. Especially, in a virtual channel DRAM, data buffer arrays can be disposed adjacent to the sense amplifier block without interference with the word line activation block.